qick.ip
Support classes for dealing with FPGA IP blocks.
Classes
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Parses the HWH XML file to extract information on the buses connecting IP blocks. |
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Dummy superclass for firmware IP blocks without register access (i.e. |
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Stores the configuration constants for a firmware IP block. |
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Provides information about the connections between IP blocks, extracted from the HWH file. |
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Parses the HWH XML file to extract information on the nets connecting IP blocks. |
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Base class for firmware IP drivers (classes that provide access to IP registers). |
- class qick.ip.DummyIP(description)[source]
Bases:
objectDummy superclass for firmware IP blocks without register access (i.e. that don’t inherit from SocIP or DefaultIP). Those classes should inherit from (QickIP, DummyIP) in that order. THis ensures that this class is last in the method resolution order.
The purpose of this class is to eat the
descriptionparameter before the MRO reachesobject.__init__(). Inspired by https://stackoverflow.com/questions/74350679/python-mixins-how-to-deal-with-args-kwargs-when-calling-super
- class qick.ip.QickIP(description)[source]
Bases:
objectStores the configuration constants for a firmware IP block. Configuration constants are accessed as dictionary items.
- class qick.ip.SocIP(*args: Any, **kwargs: Any)[source]
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Base class for firmware IP drivers (classes that provide access to IP registers). Registers are accessed as attributes.
Classes that extend a Xilinx driver will inherit from both this class and the Xilinx class. They should inherit from (SocIP, XilinxDriver) in that order. This ensures that DefaultIP (which does not support cooperative multiple inheritance) is last in the method resolution order.
- class qick.ip.QickMetadata(soc)[source]
Bases:
objectProvides information about the connections between IP blocks, extracted from the HWH file. The HWH parser is very different between PYNQ 2.6/2.7 and 3.0+, so this class serves as a common interface.
- get_fclk(blockname, portname)[source]
Find the frequency of a clock port. This returns whatever value is in the HWH file, and does not reflect software changes to the frequency after the bitstream was loaded.
- get_param(blockname, parname)[source]
Find the value of an IP parameter. This works for all IPs, including those that do not show up in ip_dict because they’re not addressable.
- trace_back(start_block, start_port, goal_types)[source]
Follow the AXI-Stream bus backwards from a given block and port. Raise an error if none of the requested IP types is found. Return None if we run into an unconnected input port.
- Parameters:
- Returns:
str – The fullpath for the block we found.
str – The output port on the block we found.
str – The IP type we found.
- trace_forward(start_block, start_port, goal_types)[source]
Follow the AXI-Stream bus forwards from a given block and port. If a broadcaster is encountered, follow all outputs. Raise an error if !=1 matching block is found.
- Parameters:
- Returns:
str – The fullpath for the block we found.
str – The input port on the block we found.
str – The IP type we found.
- list_outputs(block, port, goal_types)[source]
Given a port that might go directly to one block or be broadcast to multiple blocks, return a list of (block, port, blocktype) for the destination blocks.
- trace_dma(direction, start_block, start_port)[source]
Trace back the data path for a block that is fed by a DMA, possibly through a switch.
- Parameters:
- Returns:
str – fullpath for the DMA block
str – fullpath for the switch block, None if there is no switch
int – switch port, None if there is no switch
- trace_clk_back(start_block, start_port)[source]
Follow the clock backwards from a given block and port. Compute the clock source, the frequency, and any limits imposed by the clock path. Because it traces the clock back to its source, the frequency accounts for software changes.
The clock source is assumed to be the Zynq PS or the RF data converter. Raise an error if the clock can’t be traced back to either of those sources.
The clock path may pass through clocking wizards, which multiply the clock and impose limits on the frequency range.
- Parameters:
- Returns:
source: The clock source (‘PS’, ‘dac’, ‘adc’), and the channel number. f_clk: The clock frequency that the block sees (MHz). Accounts for clock multipliers between the source and the given block, and for software changes to the source frequency. src_range: None, or bounds (MHz) on the source clock’s frequency.
- Return type: